爱华网//add the pos SCL to clear the bit,or,it will hold thedata_cnt to be 1 and dont add up
always @(negedge SDA_in or negedgeSCL)
begin
if (!nrst)
trans_start<=1'b0;
else if (SCL)
trans_start<=1'b1;// Pos SCL @negedge SDA
else
trans_start<=1'b0;
end
NAME
ELAB-300 (error) %s Cannot test variable '%s' because it was not inthe
event expression or with wrong polarity.
DESCRIPTION
You receive this error message when the outermost ifstatement in the
always blocktests someother variablethat does not appear in a
posedge or negedge expression or with wrongpolarity. Whenan always
block's sensitivitylist containsmore than one posedge or negedge
expression, the Presto HDL Compiler assumes that oneexpr ession repre-
sents the clock, and anyremaining expressions represent asynchronous
sets or resets. For each set orreset condition,the always block
should contain an if statement that tests it.
